A high-level environment for FPGA neural network implementation

Benbouchama, Cherrad, Tadjine, Mohamed and Bouridane, Ahmed (2009) A high-level environment for FPGA neural network implementation. International Review of Electrical Engineering, 4 (6). pp. 1243-1247. ISSN 1827-6660

Full text not available from this repository. (Request a copy)
Official URL: http://www.praiseworthyprize.org/latest_issues/IRE...

Abstract

This work aims at the realization of a high-level environment to facilitate and accelerate the neural network implementation on FPGAs. A parameterizable tool was designed to generate a neural multi-layer network implementation through the use of Handel-C language. The algorithm used for the training is the back-propagation. The tools of implementation and synthesis are the DK of Celoxica and the ISE of Xilinx. The targeted components are XCV2000 on Celoxica RC1000 board and XC2V1000 on RC200. Experimental evaluations are presented to demonstrate the validity of the design.

Item Type: Article
Uncontrolled Keywords: FPGA; Handel-C; Neural networks; Parameterizable implementation
Subjects: G400 Computer Science
G600 Software Engineering
Department: Faculties > Engineering and Environment > Computer and Information Sciences
Depositing User: Becky Skoyles
Date Deposited: 23 Jan 2015 15:43
Last Modified: 10 Aug 2015 11:25
URI: http://nrl.northumbria.ac.uk/id/eprint/20492

Actions (login required)

View Item View Item

Downloads

Downloads per month over past year

View more statistics


Policies: NRL Policies | NRL University Deposit Policy | NRL Deposit Licence