A scalable and embedded FPGA architecture for efficient computation of grey level co-occurrence matrices and Haralick textures features

Siéler, Loic, Tanougast, Camel and Bouridane, Ahmed (2010) A scalable and embedded FPGA architecture for efficient computation of grey level co-occurrence matrices and Haralick textures features. Microprocessors and Microsystems, 34 (1). pp. 14-24. ISSN 0141-9331

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Abstract

This paper presents a novel and optimized embedded architecture based FPGA for an efficient and fast computation of grey level co-occurrence matrices (GLCM) and Haralick textures features for use in high throughput image analysis applications where time performance is critical. The originality of this architecture allows for a scalable and a totally embedded on Chip FPGA for the processing of large images. The architecture was implemented on Xilinx Virtex-FPGAs without the use of external memory and/or host machine. The implementations demonstrate that our proposed architecture can deliver a high reduction of the memory and FPGA logic requirements when compared with the state of the art counterparts and it also achieves much improved processing times when compared against optimized software implementation running on a conventional general purpose processor.

Item Type:	Article
Uncontrolled Keywords:	matrices, image analysis, field programmable gate arrays
Subjects:	G900 Others in Mathematical and Computing Sciences
Department:	Faculties > Engineering and Environment > Computer and Information Sciences
Depositing User:	EPrint Services
Date Deposited:	27 Jan 2010 16:50
Last Modified:	13 Oct 2019 00:30
URI:	http://nrl.northumbria.ac.uk/id/eprint/2894

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